Excellent - and thanks Mitchell Gant for the schematics +1
Well I spent a little bit more time on my set last night and here's where I got to
1. Connecting up a logic probe
Quick note for my future self, but you can use the big capacitors at the edge of the Video board to provide a good +5V and GND for the logic probe to use
2. Test Z80 Reset signal
So I logic probed pin 26 on the two Z80s (one on each board) and when turning the power supply on checked that they went through their correct power on process which is:
- Initial Low to reset chip (it's active low)
- Then High to let chip run
- Stay High
Both chips went through these processes correctly so that was a good start
3. Test Address and Data signals on EPROM groups
The EPROMs on the boards are grouped together based on their functions and cross referencing the Slap Fight driver in Mame
here I worked out that the groupings are as follows:
CPU Board
A77_02 = Sound
A77_09, A77_10, A77_11, A77_12 = Sprites (confirmed in repair log referenced above)
Video Board
A77_00, A77_01 = Main CPU
A77_05, A77_06, A77_07, A77_08 = Tiles (from Mame driver)
A77_03, A77_04 = Chars (from Mame driver
So next step was to test the address and data lines on each 'group' of EPROMs and see if they are getting data as expected (pulsing High / Low signals)
4. Sprites (A9, A10, A11, A12)
From a
video I had seen online about another Slap Fight repair, in their case the 74LS32 chips on the CPU board up by position 11 had blown the 4 x 74LS166AP parallel load, serial out 8bit shift registers which power the sprite ROM causing the clock signal shorted high (74LS166AP)
So I ran the probe across these 27128 chips and found that a number of the address registers where showing no state (neither High or Low)
[font="Courier New, Courier, mono"]27128[/font]
[font="Courier New, Courier, mono"]
[/font]
[font="Courier New, Courier, mono"]H Vpp Vcc H[/font]
[font="Courier New, Courier, mono"]H A12 /PGM H[/font]
[font="Courier New, Courier, mono"]H A7 A13 H[/font]
[font="Courier New, Courier, mono"]H A6 A8 L[/font]
[font="Courier New, Courier, mono"]H A5 A9 L[/font]
[font="Courier New, Courier, mono"]X A4 A11 H[/font]
[font="Courier New, Courier, mono"]X A3 /OE L[/font]
[font="Courier New, Courier, mono"]X A2 A10 H[/font]
[font="Courier New, Courier, mono"]X A1 /CE L[/font]
[font="Courier New, Courier, mono"]HL A0 D7 HL[/font]
[font="Courier New, Courier, mono"]HL D0 D6 HL[/font]
[font="Courier New, Courier, mono"]HL D1 D5 HL[/font]
[font="Courier New, Courier, mono"]HL D2 D4 HL[/font]
[font="Courier New, Courier, mono"]L GND D3 HL[/font]
I piggy backed some 74LS32 chips on top of the two 74LS32 chips at position 11 on the CPU board, but no luck so I'm going to order some 74LS166 chips and try piggy backing those. In the mean time I can start probe testing them too to see if they are sending out signals correctly
5. Audio (A2)
The 2nd part of the board self test is the AUDIO test, and as we can see that the self test is running by pulling out the board interconnectors I wondered if this may also be a problem
[font="Courier New, Courier, mono"]2764[/font]
[font="Courier New, Courier, mono"]
[/font]
[font="Courier New, Courier, mono"]H Vpp Vcc H[/font]
[font="Courier New, Courier, mono"]X A12 /PGM H[/font]
[font="Courier New, Courier, mono"]XD A7 N/C H[/font]
[font="Courier New, Courier, mono"]HL A6 A8 HL[/font]
[font="Courier New, Courier, mono"]HL A5 A9 X[/font]
[font="Courier New, Courier, mono"]HL A4 A11 X[/font]
[font="Courier New, Courier, mono"]HL A3 /OE L[/font]
[font="Courier New, Courier, mono"]HL A2 A10 X[/font]
[font="Courier New, Courier, mono"]HL A1 /CE X[/font]
[font="Courier New, Courier, mono"]X A0 D7 HL[/font]
[font="Courier New, Courier, mono"]HL D0 D6 HL[/font]
[font="Courier New, Courier, mono"]HL D1 D5 HL[/font]
[font="Courier New, Courier, mono"]HL D2 D4 HL[/font]
[font="Courier New, Courier, mono"]L GND D3 HL[/font]
So here again we appear to have address problems (A0, A7, A9, A10, A11, A12) so I tested the connectivity of the EPROM pins to their corresponding solder on the bottom of the board, and they all appear fine
Chip Enable is also NOT Low here which means the chip isn't enabled so could be why the self test just freezes
6. Main CPU (A0, A1)
All fine - phew! At least something is OK
[font="Courier New, Courier, mono"]27128[/font]
[font="Courier New, Courier, mono"]
[/font]
[font="Courier New, Courier, mono"]Vpp Vcc[/font]
[font="Courier New, Courier, mono"]A12 /PGM[/font]
[font="Courier New, Courier, mono"]A7 A13[/font]
[font="Courier New, Courier, mono"]A6 A8[/font]
[font="Courier New, Courier, mono"]A5 A9[/font]
[font="Courier New, Courier, mono"]A4 A11[/font]
[font="Courier New, Courier, mono"]A3 /OE[/font]
[font="Courier New, Courier, mono"]A2 A10[/font]
[font="Courier New, Courier, mono"]A1 /CE[/font]
[font="Courier New, Courier, mono"]A0 D7[/font]
[font="Courier New, Courier, mono"]D0 D6[/font]
[font="Courier New, Courier, mono"]D1 D5[/font]
[font="Courier New, Courier, mono"]D2 D4[/font]
[font="Courier New, Courier, mono"]GND D3[/font]
7. Chars (A3, A4)
All fine
[font="Courier New, Courier, mono"]2764[/font]
[font="Courier New, Courier, mono"]
[/font]
[font="Courier New, Courier, mono"]H Vpp Vcc H[/font]
[font="Courier New, Courier, mono"]HL A12 /PGM H[/font]
[font="Courier New, Courier, mono"]HL A7 N/C L[/font]
[font="Courier New, Courier, mono"]HL A6 A8 HL[/font]
[font="Courier New, Courier, mono"]HL A5 A9 HL[/font]
[font="Courier New, Courier, mono"]HL A4 A11 HL[/font]
[font="Courier New, Courier, mono"]HL A3 /OE L[/font]
[font="Courier New, Courier, mono"]HL A2 A10 HL[/font]
[font="Courier New, Courier, mono"]HL A1 /CE L[/font]
[font="Courier New, Courier, mono"]HL A0 D7 HL[/font]
[font="Courier New, Courier, mono"]HL D0 D6 HL[/font]
[font="Courier New, Courier, mono"]HL D1 D5 HL[/font]
[font="Courier New, Courier, mono"]HL D2 D4 HL[/font]
[font="Courier New, Courier, mono"]L GND D3 HL[/font]
8. Tiles (A5, A6, A7, A8)
Again some problems here, but only aroudn the very high Address Registers (A11, A12, A13) so I'll try and trace back what is running those.
[font="Courier New, Courier, mono"]27128[/font]
[font="Courier New, Courier, mono"]
[/font]
[font="Courier New, Courier, mono"]L Vpp Vcc H[/font]
[font="Courier New, Courier, mono"]X A12 /PGM X[/font]
[font="Courier New, Courier, mono"]LH A7 A13 X[/font]
[font="Courier New, Courier, mono"]LH A6 A8 HL[/font]
[font="Courier New, Courier, mono"]LH A5 A9 HL[/font]
[font="Courier New, Courier, mono"]LH A4 A11 X[/font]
[font="Courier New, Courier, mono"]LH A3 /OE L[/font]
[font="Courier New, Courier, mono"]LH A2 A10 HL[/font]
[font="Courier New, Courier, mono"]LH A1 /CE L[/font]
[font="Courier New, Courier, mono"]LH A0 D7 HL[/font]
[font="Courier New, Courier, mono"]LH D0 D6 HL[/font]
[font="Courier New, Courier, mono"]LH D1 D5 HL[/font]
[font="Courier New, Courier, mono"]LH D2 D4 HL[/font]
[font="Courier New, Courier, mono"]L GND D3 HL[/font]
More updates as I get some time but hoping the the 74LS166 chips will help fix up the Sprite EPROM problems
